High-k layer chamfering to prevent oxygen ingress in replacement metal gate (rmg) process

ABSTRACT

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a divisional of U.S. patent application Ser.No. 14/985,733 filed Dec. 31, 2015, entitled “HIGH-K LAYER CHAMFERING TOPREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS,” thecomplete disclosure of which is expressly incorporated herein byreference in its entirety for all purposes.

FIELD

The present disclosure relates generally to semiconductor devices andfabrication methods, and more specifically, to field effect transistor(FET) structures and methods of fabrication thereof.

BACKGROUND

In the Replacement Metal Gate (RMG) process, oxygen ingress during hightemperature processing is a common issue causing threshold voltage(V_(t)) to roll up in n-type FETs (NFETs) and roll down in p-type FETs(PFETs). It is also well known that high-K metal oxides (dielectricconstant higher than SiO₂) have ionic bonds and tend to transport oxygenvia oxygen vacancies when in contact with a deposited oxide material andsubjected to a high temperature annealing process. In thestate-of-the-art RMG flow, the high-K is in contact with deposited filmsin the middle-of-the-line (MOL), and could be causing the short-channelV_(t) shift observed in RMG devices.

SUMMARY

Principles of the present disclosure provide techniques for high-K layerchamfering to prevent oxygen ingress in the replacement metal gate (RMG)process.

In one aspect, an exemplary method includes providing a semiconductorstructure including a semiconductor substrate having an outer surface; aplurality of oxide regions, located outward of the outer surface of thesemiconductor substrate, and defining a plurality ofmetal-gate-stack-receiving cavities; and a liner interspersed betweenthe plurality of oxide regions and the semiconductor substrate andbetween the plurality of oxide regions and the plurality ofmetal-gate-stack-receiving cavities. A further step includes depositinga layer of high-K material over the semiconductor structure, includingon outer surfaces of the plurality of oxide regions, outer edges of theliner, on walls of the plurality of metal-gate-stack-receiving cavities,and on the outer surface of the semiconductor substrate within theplurality of metal-gate-stack-receiving cavities. A further stepincludes chamfering the layer of high-K material to remove same from theouter surfaces of the plurality of oxide regions, the outer edges of theliner, and partially down the walls of the plurality ofmetal-gate-stack-receiving cavities, to obtain a first intermediatestructure.

In another aspect, an exemplary semiconductor structure includes asemiconductor substrate having an outer surface; a plurality of metalgate stacks located outward of the outer surface of the semiconductorsubstrate; a plurality of oxide regions, located outward of the outersurface of the semiconductor substrate, and interspersed between theplurality of metal gate stacks; a liner interspersed between theplurality of oxide regions and the semiconductor substrate and betweenthe plurality of oxide regions and the plurality of metal gate stacks;and a plurality of high-K layers separating the plurality of metal gatestacks from the semiconductor substrate and separating the plurality ofmetal gate stacks from the plurality of oxide regions. The plurality ofoxide regions and the plurality of metal gate stacks extend outwardly afirst height from the semiconductor substrate, and the plurality ofhigh-K layers extend outwardly a second height from the semiconductorsubstrate. The second height is less than the first height.

As used herein, “facilitating” an action includes performing the action,making the action easier, helping to carry the action out, or causingthe action to be performed. Thus, by way of example and not limitation,instructions executing on one processor might facilitate an actioncarried out by instructions executing on a remote processor, by sendingappropriate data or commands to cause or aid the action to be performed.For the avoidance of doubt, where an actor facilitates an action byother than performing the action, the action is nevertheless performedby some entity or combination of entities.

Substantial beneficial technical effects are provided. For example, oneor more embodiments advantageously reduce or eliminate undesirablethreshold voltage changes in the Replacement Metal Gate (RMG) process,caused by oxygen ingress during high temperature processing.

These and other features and advantages of the present disclosure willbecome apparent from the following detailed description of illustrativeembodiments thereof, which is to be read in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows FETs produced by an RMG process in accordance with theprior art;

FIG. 2 shows FETs produced by an RMG process in accordance with anaspect of the disclosure;

FIG. 3 shows an initial structure with a poly open chemical mechanicalplanarization, in accordance with an aspect of the disclosure;

FIG. 4 shows flowable oxide (FOX) deposition or high densityplasma-chemical vapor deposition (HDP-CVD) of oxide over the structureof FIG. 3, followed by chemical-mechanical polishing (CMP), inaccordance with an aspect of the disclosure;

FIG. 5 shows removal of the nitride cap from the structure of FIG. 4, inaccordance with an aspect of the disclosure;

FIG. 6 shows stripping dummy poly from the structure of FIG. 5, inaccordance with an aspect of the disclosure;

FIG. 7 shows deposition of high-K material over the structure of FIG. 6,in accordance with an aspect of the disclosure;

FIG. 8 shows Titanium Nitride (TiN) deposition over the structure ofFIG. 7, in accordance with an aspect of the disclosure;

FIG. 9 shows filling and recessing with an organic dielectric layer(ODL) for the chamfering process, over the structure of FIG. 8, inaccordance with an aspect of the disclosure;

FIG. 10 shows chamfering the TiN and high-K material of the structure ofFIG. 9, in accordance with an aspect of the disclosure;

FIG. 11 shows stripping the ODL off the structure of FIG. 10, inaccordance with an aspect of the disclosure;

FIG. 12 shows deposition of amorphous silicon (aSi) over the structureof FIG. 11, in accordance with an aspect of the disclosure;

FIG. 13 shows stripping off the aSi and TiN from the structure of FIG.12, in accordance with an aspect of the disclosure;

FIG. 14 shows gate stack metals deposition (TiN and Al-doped titaniumcarbide (TiAlC)) over the structure of FIG. 13, in accordance with anaspect of the disclosure;

FIG. 15 shows chamfering of the TiN and TiAlC of the structure of FIG.14, in accordance with an aspect of the disclosure;

FIG. 16 shows wetting TiN deposition over the structure of FIG. 15, inaccordance with an aspect of the disclosure;

FIG. 17 shows tungsten (W) deposition over the structure of FIG. 16, inaccordance with an aspect of the disclosure;

FIG. 18 shows CMP of the tungsten of FIG. 17, resulting in the finalstructure of FIG. 2, in accordance with an aspect of the disclosure;

FIG. 19 shows a detail of the final structure of FIGS. 2 and 18,including source-drain regions; and

FIG. 20 shows exemplary details of chamfering, in accordance with anaspect of the disclosure.

DETAILED DESCRIPTION

As noted, in the Replacement Metal Gate (RMG) process, oxygen ingressduring high temperature processing is a common issue causing thresholdvoltage (V_(t)) to roll up in n-type FETs (NFETs) and roll down inp-type FETs (PFETs). It is also well known that high-K metal oxides(dielectric constant higher than SiO₂) have ionic bonds and tend totransport oxygen via oxygen vacancies when in contact with a depositedoxide material and subjected to a high temperature annealing process. Inthe state-of-the-art RMG flow, the high-K is in contact with depositedfilms in the middle-of-the-line (MOL), and could be causing theshort-channel V_(t) shift observed in RMG devices.

FIG. 1 shows FETs produced by an RMG process in accordance with theprior art. Note the metal gate stacks 197. Source and drain regions willbe located in the substrate 101 on either side of the gate structures ina well-known manner, and are omitted to avoid clutter. Substrate 101 hasa SiN liner 105. Note oxide region 111 and spacers 107. Each gate stackarea includes high-K material 115, first TiN layer 123, TiAlC layer 125,second TiN layer 127, and tungsten contact 129. During processing inaccordance with the prior art, prior to planarization, the high-K 115 isin contact with high-density-plasma-deposited (HDP) oxide 111. This isan intermediate condition not visible in the view of FIG. 1, but isaddressed in one or more embodiments as discussed below with respect toFIGS. 8-10. Regions 199 show a resulting potentially problematic area inprior art techniques.

Since the HDP oxide is deposited in the later stages of the RMG process,it cannot be annealed at high temperatures for long times to densify theoxide without significantly degrading the junctions. One or moreembodiments advantageously disconnect the high-K layer from the HDPoxide prior to the high temperature reliability annealing process.Indeed, one or more embodiments chamfer the high-K layer prior todepositing the TiN and aSi layers for reliability annealing, so thatthere is no path for oxygen ingress during the high temperatureprocessing.

FIG. 2 shows FETs produced by an RMG process in accordance with anaspect of the disclosure. Note the metal gate stacks 397. A substrate301 has a SiN liner 305. Note oxide region 311 and spacers 307. Eachgate stack area includes high-K material 315, first TiN layer 323, TiAlClayer 325, second TiN layer 327, and tungsten contact 329. The high-K315 is chamfered, as discussed below, so that there is no path foroxygen ingress during the high temperature processing.

FIG. 3 shows an initial structure with a SiN liner on dummy gates, inaccordance with an aspect of the disclosure. In particular, FIG. 3 showsa substrate 301 with dummy gate structures including, e.g., “dummy”polysilicon 303; the substrate can be, for example, asilicon-on-insulator (SOI) substrate or bulk substrate with either aplanar structure or a FIN structure for the channel area of thetransistors. Note the SiN liner 305; spacer 307; and hardmask 309 todefine the gate structure.

FIG. 4 shows flowable oxide (FOX) deposition or high densityplasma-chemical vapor deposition (HDP-CVD) of silicon dioxide (depositedmaterial generally 311) over the structure of FIG. 3, followed bychemical-mechanical polishing (CMP), in accordance with an aspect of thedisclosure. The skilled artisan will appreciate that polymer hydrogensilsesquioxane (HSQ) solution in methyl isobutyl ketone (MIBK),commercially known as FOX (flowable oxide), is an alternative materialto silicon dioxide obtained by chemical deposition.

FIG. 5 shows removal of the hardmask 309 from the structure of FIG. 4,in accordance with an aspect of the disclosure. Hardmask 309 can beremoved, for example, by CMP, reactive ion etching, or wet etching.

FIG. 6 shows stripping dummy poly from the structure of FIG. 5, inaccordance with an aspect of the disclosure. The stripping of dummy polycan be done with wet etching (e.g. TMAH, diluted NH4OH) or reactive ionetching. Cavities 395 are discussed below.

FIG. 7 shows deposition of high-K material 315 over the structure ofFIG. 6, in accordance with an aspect of the disclosure. Hf-based high-Kmaterials are typically deposited by atomic layer deposition (ALD) orchemical vapor deposition (CVD).

FIG. 8 shows deposition of Titanium Nitride (TiN) 317 over the structureof FIG. 7, in accordance with an aspect of the disclosure. ALD or CVDcan be used for TiN deposition, for example. Note contact of layer 315and oxide 311, which has proven problematic in prior art techniques butis addressed in one or more embodiments as discussed just below withregard to FIGS. 9 and 10.

FIG. 9 shows filling and recessing with an organic dielectric layer(ODL) 319 for the chamfering process, over the structure of FIG. 8, inaccordance with an aspect of the disclosure.

FIG. 10 shows chamfering the TiN 317 and high-K material 315 of thestructure of FIG. 9, in accordance with an aspect of the disclosure. Thehigh-K material 315 and TiN 317 can be chamfered using, for example,reactive-ion etching (ME) or the well-known wet SC1 process.

FIG. 11 shows stripping the ODL off the structure of FIG. 10, inaccordance with an aspect of the disclosure.

FIG. 12 shows deposition of amorphous silicon (aSi) 321 over thestructure of FIG. 11, in accordance with an aspect of the disclosure, inpreparation for reliability annealing. A CVD process is typically used.High temperature anneal (>950 C, 0 (spike)-5 sec) is performed at thisstep with the presence of aSi, in one or more embodiments.

FIG. 13 shows stripping off the aSi and TiN from the structure of FIG.12, in accordance with an aspect of the disclosure. One or morenon-limiting exemplary embodiments employ wet etching (TMAH, or dilutedNH4OH) or reactive etching for aSi removal, and SC1 for TiN removal.

FIG. 14 shows gate stack metals deposition (TiN 323 and titanium carbide(TiC) 325) over the structure of FIG. 13, in accordance with an aspectof the disclosure (ALD or CVD can be employed, for example).

FIG. 15 shows chamfering of the TiN and TiAlC of the structure of FIG.14, in accordance with an aspect of the disclosure, following the usualRMG flow.

FIG. 16 shows deposition of wetting TiN 327 over the structure of FIG.15, in accordance with an aspect of the disclosure (ALD or CVD can beemployed, for example, and TaN is an alternative material).

FIG. 17 shows deposition of tungsten (W) 329 over the structure of FIG.16, in accordance with an aspect of the disclosure (e.g., via CVD).

FIG. 18 shows CMP of the tungsten of FIG. 17, resulting in the finalstructure of FIG. 2, in accordance with an aspect of the disclosure.

FIG. 19 shows a detail of the final structure of FIGS. 2 and 18,including appropriately doped source-drain regions 393 located in thesubstrate 301 on either side of the gate stack 397 in a well-knownmanner.

One or more embodiments improve upon the techniques disclosed in U.S.Pat. No. 8,999,831 issued on 7 Apr. 2015 (expressly incorporated hereinby reference in its entirety for all purposes), which includes a hightemperature anneal with the presence of dummy amorphous Si layer in RMGflow. One or more embodiments advantageously perform High-k chamferingor recessing prior to this high temperature anneal. This enablesdisconnecting a high-k path between the field oxide and the activedevice area at the time of the high temperature anneal, resulting insuppression of unwanted migration of oxygen via the High-k path. One ormore embodiments do not require oxygen scavengers, oxidation masking, orother undesirable extra layers.

Given the discussion thus far, and referring to FIG. 2, it will beappreciated that, in general terms, an exemplary semiconductorstructure, according to an aspect of the disclosure, includes asemiconductor substrate 301 having an outer surface; a plurality ofmetal gate stacks 397 located outward of the outer surface of thesemiconductor substrate; and a plurality of oxide regions 311. The oxideregions 311 are located outward of the outer surface of thesemiconductor substrate, and are interspersed between the plurality ofmetal gate stacks 397. Also included is a liner 305 interspersed betweenthe plurality of oxide regions 311 and the semiconductor substrate 301and between the plurality of oxide regions 311 and the plurality ofmetal gate stacks 397. A plurality of high-K layers 315 separate theplurality of metal gate stacks 397 from the semiconductor substrate 301and separate the plurality of metal gate stacks 397 from the pluralityof oxide regions 311. The plurality of oxide regions 311 and theplurality of metal gate stacks 397 extend outwardly a first height fromthe semiconductor substrate 301. The plurality of high-K layers 315extend outwardly a second height from the semiconductor substrate 301.The second height is less than the first height.

Referring now to FIG. 20, in one or more embodiments, the chamferingamount is more than the polishing margin for the CMP process but not somuch as to reach the FIN top surface. In particular, as noted above, thesubstrate 301 can be, for example, a silicon-on-insulator (SOI)substrate or bulk substrate with either a planar structure or a FINstructure 391 for the channel area of the transistors. FIG. 20 shows anon-limiting FIN example. View 387 is parallel to the FIN while view 389is vertical to the FIN(s). The FIN 391 is located within the gate trenchand has a top surface above the substrate a fin height h_(f). The gateheight is h_(g). The chamfer amount for the high-K 315 is h_(c). Thechamfer amount h_(c) is greater than zero (and, practically, greaterthan the CMP polish margin) but is not so much as to reach the topsurface of the FIN (i.e., is less than h_(g)−h_(f)).

Thus, in some instances, the structure further includes a plurality ofFINS 391 intermediate the plurality of high-K layers 315 and thesubstrate 301, and the second height is such that the plurality ofhigh-K layers extend outwardly beyond the plurality of FINS.

The substrate includes, for example, a silicon-on-insulator substrate ora bulk substrate.

The oxide regions include, for example, silicon dioxide or flowableoxide.

The liner includes, for example, silicon nitride.

The high-K layers include, for example, a metal oxide with a dielectricconstant greater than that of silicon dioxide.

Furthermore, given the discussion thus far, and referring to FIG. 6, itwill be appreciated that, in general terms, an exemplary method,according to another aspect of the disclosure, includes the step ofproviding a semiconductor structure, The semiconductor structure in turnincludes a semiconductor substrate 301 having an outer surface; aplurality of oxide regions 311, located outward of the outer surface ofthe semiconductor substrate, and defining a plurality ofmetal-gate-stack-receiving cavities 395; and a liner 305 interspersedbetween the plurality of oxide regions 311 and the semiconductorsubstrate 301 and between the plurality of oxide regions 311 and theplurality of metal-gate-stack-receiving cavities 395.

As best seen in FIG. 7, a further step includes depositing a layer ofhigh-K material 315 over the semiconductor structure, including on outersurfaces of the plurality of oxide regions 311, outer edges of the liner305, on walls of the plurality of metal-gate-stack-receiving cavities395, and on the outer surface of the semiconductor substrate 301 withinthe plurality of metal-gate-stack-receiving cavities 395.

As best seen in FIG. 10, a still further step includes chamfering thelayer of high-K material 315 to remove same from the outer surfaces ofthe plurality of oxide regions 311, the outer edges of the liner 305,and partially down the walls of the plurality ofmetal-gate-stack-receiving cavities 395, to obtain a first intermediatestructure.

The chamfering may be, for example, by an amount greater than a chemicalmechanical polishing margin, but not so much as to reach a FIN surfaceunderlying the high-K material.

In some instances, further steps include, as best seen in FIG. 12,depositing amorphous silicon 321 over the first intermediate structureto obtain a second intermediate structure, and carrying out reliabilityannealing on the second intermediate structure; and, as best seen inFIGS. 13-18, removing the amorphous silicon, and forming a plurality ofmetal gate stacks in the plurality of metal-gate-stack-receivingcavities.

The methods as described above are used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A method comprising: providing a semiconductorstructure comprising: a semiconductor substrate having an outer surface;a plurality of oxide regions, located outward of said outer surface ofsaid semiconductor substrate, and defining a plurality ofmetal-gate-stack-receiving cavities; and a liner interspersed betweensaid plurality of oxide regions and said semiconductor substrate andbetween said plurality of oxide regions and said plurality ofmetal-gate-stack-receiving cavities; depositing a layer of high-Kmaterial over said semiconductor structure, including on outer surfacesof said plurality of oxide regions, outer edges of said liner, on wallsof said plurality of metal-gate-stack-receiving cavities, and on saidouter surface of said semiconductor substrate within said plurality ofmetal-gate-stack-receiving cavities; and chamfering said layer of high-Kmaterial to remove same from said outer surfaces of said plurality ofoxide regions, said outer edges of said liner, and partially down saidwalls of said plurality of metal-gate-stack-receiving cavities, toobtain a first intermediate structure.
 2. The method of claim 1, whereinsaid chamfering comprises chamfering an amount greater than a chemicalmechanical polishing margin.
 3. The method of claim 2, wherein saidchamfering further comprises chamfering such that said amount greaterthan said chemical mechanical polishing margin is also less than a FINsurface underlying said high-K material.
 4. The method of claim 2,further comprising: depositing amorphous silicon over said firstintermediate structure to obtain a second intermediate structure;carrying out reliability annealing on said second intermediatestructure; removing said amorphous silicon; and forming a plurality ofmetal gate stacks in said plurality of metal-gate-stack-receivingcavities.